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ltc3863 1 3863f for more information www.linear.com/3863 typical application features description 60v low i q inverting dc/dc controller the lt c ? 3863 is a robust, inverting dc/dc pmos control - ler optimized for automotive and industrial applications. it drives a p-channel power mosfet to generate a negative output and requires just a single inductor to complete the circuit. output voltages from C0.4v to C150v are typically achievable with higher voltages possible, only limited by external components. the ltc3863 offers excellent light load efficiency, draw - ing only 70a quiescent current in a user programmable burst mode operation. its peak current mode, constant frequency pwm architecture provides for good control of switching frequency and output current limit. the switch - ing frequency can be programmed from 50khz to 850khz with an external resistor and can be synchronized to an external clock from 75khz to 750khz. the ltc3863 offers programmable soft-start or output tracking. safety features include overvoltage, overcurrent and short-circuit protection including frequency foldback. the ltc3863 is available in thermally enhanced 12-lead msop and 3mm 4mm dfn packages. 4.5v to 16v input, C5v/1.7a output, 350khz inverting converter applications n wide operating v in range: 3.5v to 60v n wide negative v out range: C0.4v to beyond C150v n low operating i q = 70a n strong high voltage mosfet gate driver n constant frequency current mode architecture n verified fmea for adjacent pin open/short n selectable high efficiency burst mode ? operation or pulse-skipping mode at light loads n programmable fixed frequency: 50khz to 850khz n phase-lockable frequency: 75khz to 750khz n accurate current limit n programmable soft-start or voltage tracking n internal soft-start guarantees smooth start-up n low shutdown i q = 7a n available in small 12-lead thermally enhanced msop and dfn packages n industrial and automotive power supplies n telecom power supplies n distributed power systems l , lt, ltc, ltm, opti-loop, linear technology, burst mode and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5731694. efficiency 350khz 16m 10h si7129 b540c cap 0.47f 10f 25v 2 pgnd ltc3863 3863 ta01a ss ith freq sgnd run v in pllin/mode sense gate v fbn v fb 14.7k 61.9k 511k 33f 2 v out ?5v 1.7a 80.6k 68pf v in 4.5v to 16v 27nf 150f 16v 2 + 100f 20v + load current (a) 0.002 40 efficiency (%) power loss (w) 60 90 80 0.02 0.2 2 3863 ta01b 20 30 50 70 10 0 4 6 9 8 2 3 5 7 1 0 efficiency power loss v in = 12v v out = ?5v pulse-skipping mode burst mode operation
ltc3863 2 3863f for more information www.linear.com/3863 pin configuration absolute maximum ratings input supply voltage (v in ) ......................... C0.3v to 65v v in -v sense voltage ...................................... C0.3v to 6v v in -v cap voltage ........................................ C0.3v to 10v run voltage ............................................... C0.3v to 65v v fbn , pllin/mode voltages ....................... C0.3v to 6v ss, ith, freq, v fb voltages ........................ C0.3v to 5v (note 1) 12 11 10 9 8 7 13 pgnd 1 2 3 4 5 6 gate v in sense cap run v fbn pllin/mode freq sgnd ss v fb ith top view de package 12-lead (4mm 3mm) plastic dfn t jmax = 150c, ja = 43c/w, jc = 5.5c/w exposed pad (pin 13) is pgnd, must be soldered to pcb 1 2 3 4 5 6 pllin/mode freq sgnd ss v fb ith 12 11 10 9 8 7 gate v in sense cap run v fbn top view 13 pgnd mse package 12-lead plastic msop t jmax = 150c, ja = 40c/w, jc = 10c/w exposed pad (pin 13) is pgnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc3863emse#pbf ltc3863emse#trpbf 3863 12-lead plastic msop C40c to 125c ltc3863imse#pbf ltc3863imse#trpbf 3863 12-lead plastic msop C40c to 125c ltc3863hmse#pbf ltc3863hmse#trpbf 3863 12-lead plastic msop C40c to 150c ltc3863mpmse#pbf ltc3863mpmse#trpbf 3863 12-lead plastic msop C55c to 150c ltc3863ede#pbf ltc3863ede#trpbf 3863 12-lead (4mm 3mm) plastic dfn C40c to 125c ltc3863ide#pbf ltc3863ide#trpbf 3863 12-lead (4mm 3mm) plastic dfn C40c to 125c ltc3863hde#pbf ltc3863hde#trpbf 3863 12-lead (4mm 3mm) plastic dfn C40c to 150c ltc3863mpde#pbf ltc3863mpde#trpbf 3863 12-lead (4mm 3mm) plastic dfn C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating junction temperature range (notes 2, 3, 4) ltc3863e,i ....................................... C40c to 125c ltc3863h .......................................... C40c to 150c ltc3863mp ....................................... C55c to 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) msop package ................................................. 300c
ltc3863 3 3863f for more information www.linear.com/3863 electrical characteristics symbol parameter conditions min typ max units input supply v in input voltage operating range 3.5 60 v v uvlo undervoltage lockout (v in -v cap ) ramping up threshold (v in -v cap ) ramping down threshold hysteresis l l 3.25 3.00 3.50 3.25 0.25 3.8 3.50 v v v i q input dc supply current pulse-skipping mode pllin/mode = 0v, freq = 0v, v fb = 0.83v (no load) 0.77 1.2 ma burst mode operation pllin/mode = open, freq = 0v, v fb = 0.83 v (no load) 50 70 a shutdown supply current run = 0v 7 12 a output sensing v reg regulated feedback voltage v reg = (v fb C v fbn ) v ith = 1.2v (note 5) l 0.791 0.800 0.809 v ?v reg ?v in feedback voltage line regulation v in = 3.8v to 60v (note 5) C0.005 0.005 %/v ?v reg ?v ith feedback voltage load regulation v ith = 0.6v to 1.8v (note 5) C0.1 C0.015 0.1 % g m(ea) error amplifier transconductance v ith = 1.2v, ?i ith = 5a (note 5) 1.8 ms i fbn feedback negative input bias current C50 C10 50 na current sensing v ilim current limit threshold (v in -v sense ) v fb = 0.77v l 85 95 103 mv i sense sense pin input current v sense = v in 0.1 2 a start-up and shutdown v run run pin enable threshold v run rising l 1.22 1.26 1.32 v v runhys run pin hysteresis 150 mv i ss soft-start pin charging current v ss = 0v 10 a switching frequency and clock synchronization f programmable switching frequency r freq = 24.9k r freq = 64.9k r freq = 105k 375 105 440 810 505 khz khz khz f lo low switching frequency freq = 0v 320 350 380 khz f hi high switching frequency freq = open 485 535 585 khz f sync synchronization frequency l 75 750 khz v clk(ih) clock input high level into pllin/mode l 2 v v clk(lo) clock input low level into pllin/mode l 0.5 v f fold foldback frequency as percentage of programmable frequency v fb = 0v, v freq = 0v 18 % t on (min) minimum on- time 220 ns the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 12v, unless otherwise noted. (note 4)
ltc3863 4 3863f for more information www.linear.com/3863 symbol parameter conditions min typ max units gate driver v cap gate bias ldo output voltage (v in -v cap ) i gate = 0ma l 7.6 8.0 8.5 v v capdrop gate bias ldo dropout voltage v in = 5v, i gate = 15ma 0.2 0.5 v ?v cap(line) gate bias ldo line regulation 9v v in 60v, i gate = 0ma 0.002 0.03 %/v ? v cap ( load ) gate bias ldo load regulation load = 0ma to 20ma C3.5 % r up gate pull-up resistance gate high 2 r dn gate pull -down resistance gate low 0.9 overvoltage v fbov v fb overvoltage lockout threshold gate going high without delay, v fb(ov) -v fb(nom) in percent 10 % electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 12v, unless otherwise noted. (note 4) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: continuous operation above the specified maximum operating junction temperature may impair device reliability or permanently damage the device. note 3: the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) as follows: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance provided in the pin configuration section for the corresponding package. note 4: the ltc3863 is tested under pulsed load conditions such that t j t a . the ltc3863e is guaranteed to meet performance specifications from 0c to 85c operating junction temperature range. the ltc3863e specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3863i is guaranteed to meet performance specifications over the C40c to 125c operating junction temperature range, the ltc3863h is guaranteed over the C40c to 150c operating junction temperature range, and the ltc3863mp is guaranteed and tested over the full C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 5: the ltc3863 is tested in a feedback loop that adjust v reg or (v fb C v fbn ) to achieve a specified error amplifier output voltage (on ith pin).
ltc3863 5 3863f for more information www.linear.com/3863 typical performance characteristics transient response: pulse-skipping mode operation transient response: rising edge pulse-skipping mode operation transient response: falling edge pulse-skipping mode operation normal soft-start soft-start into a prebiased output output tracking pulse-skipping mode operation waveforms burst mode operation waveforms transient response: burst mode operation t a = 25c, unless otherwise noted. v in = 12v v out = ?5v i load = 100ma figure 7 circuit v sw 10v/div v out 50mv/div i l 500ma/div 2s/div 3863 g01 v in = 12v v out = ?5v i load = 100ma figure 7 circuit v sw 10v/div v out 50mv/div i l 500ma/div 20s/div 3863 g02 v in = 12v v out = ?5v transient = 100ma to 1.6a figure 7 circuit v out 200mv/div i load 1a/div i l 1a/div 100s/div 3863 g03 v in = 12v v out = ?5v transient = 100ma to 1.6a figure 7 circuit v out 200mv/div i load 1a/div i l 1a/div 100s/div 3863 g04 v in = 12v v out = ?5v transient = 100ma to 1.6a figure 7 circuit v out 200mv/div i load 1a/div i l 1a/div 10s/div 3863 g05 v in = 12v v out = ?5v transient = 1.6a to 100ma figure 7 circuit v out 200mv/div i load 1a/div i l 1a/div 10s/div 3863 g06 v in = 12v v out1 = 5v v out2 = ?5v i load1 = i load2 = 100ma figure 11 circuit v out1 2v/div v out2 2v/div v in 5v/div track/ss 200mv/div 1ms/div 3863 g07 v in = 12v v out1 = 5v, v out2 = ?5v pre-bias1 = 2v, pre-bias2 = ?2v i load = 50ma figure 11 circuit v out1 2v/div v out2 2v/div run 5v/div track/ss 200mv/div 1ms/div 3863 g08 v in = 12v v out1 = 5v v out2 = ?5v i load1 = i load2 = 100ma figure 11 circuit v out1 2v/div v out2 2v/div track/ss 200mv/div 20ms/div 3863 g09
ltc3863 6 3863f for more information www.linear.com/3863 typical performance characteristics burst mode input current over input voltage (no load) pulse-skipping mode input current over input voltage (no load) shutdown current over input voltage output regulation over input voltage output regulation over load current output regulation over temperature overcurrent protection short-circuit protection v in line transient behavior t a = 25c, unless otherwise noted. v in = 12v v out = ?5v i load2 = 1a to 3.2a figure 7 circuit i l 1a/div v out 500mv/div i load 1a/div 20ms/div 3863 g10 v in = 12v v out = ?5v i load2 = 1a to short-circuit figure 7 circuit i l 1a/div v out 5v/div short- circuit trigger 500s/div foldback 3863 g11 soft-start recovery c out discharge v in = 12v, surge to 48v v out = ?5v i load = 500ma figure 7 circuit gate 20v/div v out 50mv/div v in 20v/div 10ms/div 3863 g12 12v 48v v in (v) 0 110 i vin (a) 115 120 125 130 140 10 20 30 40 3863 g13 50 60 135 v in = 12v v out = ?5v i load = 0a figure 7 circuit v in (v) 0 i vin (a) 900 3863 g14 800 700 20 40 10 30 50 1000 1100 850 750 950 1050 60 v in = 12v v out = ?5v i load = 0a figure 7 circuit v in (v) 0 0 i vin (a) 5 10 15 20 30 10 20 30 40 3863 g15 50 60 25 v in = 12v figure 7 circuit v in (v) 0 ?1.0 normalized ?v out (%) ?0.5 0 0.5 1.0 10 20 30 40 3863 g16 50 60 v out = ?5v i load = 100ma nomalized at v in = 12v figure 7 circuit pulse-skipping mode burst mode operation i load (a) ?0.5 ?1.0 normalized ?v out (%) ?0.5 0 0.5 1.0 0 0.5 1.0 1.5 3863 g17 2.0 2.5 v in = 12v, v out = ?5v i load normalized at i load = 1a figure 7 circuit pulse-skipping mode burst mode operation temperature (c) ?75 normalized ?v out (%) 0.2 0.6 1.0 125 3963 g18 ?0.2 ?0.6 0 0.4 0.8 ?0.4 ?0.8 ?1.0 ?25 25 75 175 v in = 12v, v out = ?5v i load = 200ma v out nomalized to t a = 25c figure 7 circuit pulse-skipping mode burst mode operation
ltc3863 7 3863f for more information www.linear.com/3863 typical performance characteristics gate bias ldo (v in - v cap ) load regulation gate bias ldo (v in - v cap ) dropout behavior current sense voltage over ith voltage current sense voltage over temperature ss pin pull-up current over temperature run pin pull-up current over temperature free running frequency over input voltage free running frequency over temperature frequency foldback % over feedback voltage t a = 25c, unless otherwise noted. v in (v) 0 300 f (khz) 450 600 550 500 400 350 10 20 30 40 50 3863 g19 60 freq = 0v freq = open v fb (mv) 0 0 frequency foldback (%) 60 120 100 80 40 20 200 400 600 3863 g21 800 i gate (ma) 0 ?3.5 (v in - v cap ) regulation (%) ?2.0 0.5 ?1.0 ?0.5 0.0 ?1.5 ?2.5 ?3.0 5 10 15 3863 g22 20 i gate (ma) 0 ?0.5 (v in - v cap ) dropout (v) 0.1 v in = 5v ?0.1 0.0 ?0.2 ?0.3 ?0.4 5 10 15 3863 g23 20 temperature (c) ?75 90 current limit sense voltage (mv) 100 98 94 92 96 ?25 25 75 125 3863 g25 175 temperature (c) ?75 0.25 run pull-up current (a) 0.65 0.55 0.35 0.45 ?25 25 75 125 3863 g27 175 v run = 0v temperature (c) ?75 300 f (khz) 450 600 550 500 400 350 ?25 25 75 125 3864 g20 175 freq = 0v freq = open temperature (c) ?75 6 ss pull-up current (a) 14 12 8 10 ?25 25 75 125 3863 g26 175 v ss = 0v ith voltage (v) 0 ?10 current sense voltage (mv) 100 80 90 40 30 20 10 0 70 60 50 0.4 0.8 1.2 1.6 3863 g24 2 burst mode operation pulse-skipping
ltc3863 8 3863f for more information www.linear.com/3863 pin functions pllin/mode (pin 1): external reference clock input and burst mode enable/disable. when an external clock is applied to this pin, the internal phase-locked loop will synchronize the turn-on edge of the gate drive signal with the rising edge of the external clock. when no external clock is applied, this input determines the operation during light loading. floating this pin selects low i q (40a) burst mode operation. pulling to ground selects pulse-skipping mode operation. freq (pin 2): switching frequency setpoint input. the switching frequency is programmed by an external set- point resistor r freq connected between the freq pin and signal ground. an internal 20a current source creates a voltage across the external setpoint resistor to set the internal oscillator frequency. alternatively, this pin can be driven directly by a dc voltage to set the oscillator frequency. grounding selects a fixed operating frequency of 350khz. floating selects a fixed operating frequency of 535khz. sgnd (pin 3): ground reference for small-signal analog component (signal ground). signal ground should be used as the common ground for all small-signal analog inputs and compensation components. connect the signal ground to the power ground (ground reference for power components) only at one point using a single pcb trace. ss (pin 4): soft-start and external tracking input. the ltc3863 regulates the feedback voltage to the smaller of 0.8v or the voltage on the ss pin. an internal 10a pull-up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to the final regulated output voltage. alternatively, another voltage supply con - nected through a resistor divider to this pin allows the output to track the other supply during start-up. v fb (pin 5): output feedback sense. a resistor divider from the regulated output point to this pin sets the output voltage. the ltc3863 will nominally regulate v fb to the internal reference value of 0.8v. if v fb is less than 0.4v, the switching frequency will linearly decrease and fold back to about one-fifth of the internal oscillator frequency to reduce the minimum duty cycle. ith (pin 6): current control threshold and controller compensation point. this pin is the output of the error amplifier and the switching regulators compensation point. the voltage ranges from 0v to 2.9v, with 0.8v cor - responding to zero sense voltage (zero current). v fbn (pin 7): feedback input for an inverting pwm con - troller. connect v fbn to the center of a resistor divider between the output and v fb . the v fbn threshold is 0v. to defeat the inverting amplifier and use the ltc3863 as an ltc3864 (noninverting buck), tie v fbn > 2v. run (pin 8): digital run control input. a run voltage above the 1.26v threshold enables normal operation, while a voltage below the threshold shuts down the controller. an internal 0.4a current source pulls the run pin up to about 3.3v. the run pin can be connected to an external power supply up to 60v. cap (pin 9): gate driver (C) supply. a low esr ceramic bypass capacitor of at least 0.1f or 10x the effective c miller of the p-channel power mosfet, is required from v in to this pin to serve as a bypass capacitor for the internal regulator. to ensure stable low noise operation, the bypass capacitor should be placed adjacent to the v in and cap pins and connected using the same pcb metal layer. sense (pin 10): current sense input. a sense resistor, r sense , from the v in pin to the sense pin sets the maxi - mum current limit. the peak inductor current limit is equal to 95mv/r sense . for accuracy, it is important that the v in pin and the sense pin route directly to the current sense resistor and make a kelvin (4-wire) connection. v in (pin 11): chip power supply. a minimum bypass capacitor of 0.1f is required from the v in pin to power ground. for best performance use a low esr ceramic capacitor placed near the v in pin. gate (pin 12): gate drive output for external p-channel mosfet. the gate driver bias supply voltage (v in -v cap ) is regulated to 8v when v in is greater than 8v. the gate driver is disabled when (v in -v cap ) is less than 3.5v (typi - cal), 3.8v maximum in start-up and 3.25v (typical) 3.5v maximum in normal operation. pgnd (exposed pad pin 13): ground reference for power components (power ground). the pgnd exposed pad must be soldered to the circuit board for electrical contact and for rated thermal performance of the package. connect signal ground to power ground only at one point using a single pcb trace.
ltc3863 9 3863f for more information www.linear.com/3863 ? + ea (g m = 1.8ms) 0.8v en 10a logic control ldo in out pll system q s r mode/clock detect vco ov 0.88v slope compensation 3.25v gate cap ss v fbn v in ? 8v sense v in 1.26v ? + + pllin/mode pgnd c cap mp d1 0.5a uvlo r freq sgnd freq run run 0.4a 20a 3863 fd + ? ? + ? drv clock + ? + ? o.425v burst mode operation + ? ith r ith c ith1 l c ss c fb2 c in v in r sense c out v out v fb r fb1 r fb2 icmp + functional diagram
ltc3863 10 3863f for more information www.linear.com/3863 operation ltc3863 main control loop the ltc3863 is a nonsynchronous inverting pmos controller, where an inverting amplifier is used to sense the negative output voltage below ground. the ltc3863 uses a peak current mode control architecture to regulate the output. a feedback resistor, r fb1 , is placed between v out and v fbn and a second resistor, r fb2 , is placed between v fbn and and v fb . the ltc3863 has a trimmed internal reference, v ref , that is equal to (v fb C v fbn ). the output voltage is equal to C(r fb1 /r fb2 ) ? v ref where v ref is equal to 800mv in normal regulation. the ltc3863 can also be configured as a noninverting step-down buck regulator when the v fbn node is pulled greater than 2v but held less than 5v, which disables the internal inverting amplifier. a feedback resistor, r fb1 , is placed between v out and v fb and a second resistor, r fb2 , is placed between v fb and sgnd. in the noninverting buck mode the v fb input is compared to the internal reference, v ref , by a transconductance error amplifier (ea). the internal reference can be either a fixed 0.8v reference, v ref , or the voltage input on the ss pin. in normal operation v fb regulates to the internal 0.8v refer - ence voltage. the output voltage in normal regulation is equal to (r fb1 + r fb2 )/r fb2 ? 800mv. in soft-start or tracking mode when the ss pin voltage is less than the internal 0.8v reference voltage, v fb will regulate to the ss pin voltage. the error amplifier output connects to the ith (current [i] threshold [th]) pin. the voltage level on the ith pin is then summed with a slope compensation ramp to create the peak inductor current set point. the peak inductor current is measured through a sense resistor, r sense , placed across the v in and sense pins. the resultant differential voltage from v in to sense is proportional to the inductor current and is compared to the peak inductor current setpoint. during normal opera - tion the p-channel power mosfet is turned on when the clock leading edge sets the sr latch through the s input. the p-channel mosfet is turned off through the sr latch r input when the differential voltage from v in to sense is greater than the peak inductor current setpoint and the current comparator, icmp, trips high. power cap and v in undervoltage lockout (uvlo) power for the p-channel mosfet gate driver is derived from the cap pin. the cap pin is regulated to 8v below v in in order to provide efficient p-channel operation. the power for the v cap supply comes from an internal ldo, which regulates the v in -cap differential voltage. a mini - mum capacitance of 0.1f (low esr ceramic) is required between v in and cap to assure stability. for v in 8v, the ldo will be in dropout and the cap volt - age will be at ground, i.e., the v in -cap differential voltage will equal v in . if v in -cap is less than 3.25v (typical), the ltc3863 enters a uvlo state where the gate is prevented from switching and most internal circuitry is shut down. in order to exit uvlo, the v in -cap voltage would have to exceed 3.5v (typical). shutdown and soft-start when the run pin is below 0.7v, the controller and most internal circuits are disabled. in this micropower shutdown state, the ltc3863 draws only 7a. releasing the run pin allows a small internal pull-up current to pull the run pin above 1.26v and enable the controller. the run pin can be pulled up to an external supply of up to 60v or it can be driven directly by logic levels.
ltc3863 11 3863f for more information www.linear.com/3863 operation the start-up of the output voltage v out is controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the 0.8v internal reference, the v fb pin is regulated to the voltage on the ss pin. this allows the ss pin to be used to program a soft-start by connecting an external capacitor from the ss pin to signal ground. an internal 10a pull-up current charges this capacitor, creat - ing a voltage ramp on the ss pin. as the ss voltage rises from 0v to 0.8v, the output voltage v out rises smoothly from zero to its final value. alternatively, the ss pin can be used to cause the start-up of v out to track that of another supply. typically, this requires connecting the ss pin to an external resistor divider from the other supply to ground (see applications information). under shutdown or uvlo, the ss pin is pulled to ground and prevented from ramping up. if the slew rate of the ss pin is greater than 1.2v/ms, the output will track an internal soft-start ramp instead of the ss pin. the internal soft-start will guarantee a smooth start-up of the output under all conditions, including in the case of a short-circuit recovery where the output voltage will recover from near ground. light load current operation (burst mode operation or pulse-skipping mode) the ltc3863 can be enabled to enter high efficiency burst mode operation or pulse-skipping mode at light loads. to select pulse-skipping operation, tie the pllin/mode pin to signal ground. to select burst mode operation, float the pllin/mode pin. in burst mode operation, if the v fb is higher than the refer - ence voltage, the error amplifier will decrease the voltage on the ith pin. when the ith voltage drops below 0.425v, the internal sleep signal goes high, enabling sleep mode. the ith pin is then disconnected from the output of the error amplifier and held at 0.45v. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current to 70a while the load current is supplied by the output capacitor. as the output voltage and hence the feedback voltage decreases, the error amplifiers output will rise. when the output voltage drops enough, the ith pin is reconnected to the output of the error amplifier, the sleep signal goes low, and the controller resumes normal operation by turning on the external p-channel mosfet on the next cycle of the internal oscillator. in burst mode operation, the peak inductor current has to reach at least 25% of current limit for the current comparator, icmp, to trip and turn the p-channel mosfet back off, even though the ith voltage may indicate a lower current setpoint value. when the pllin/mode pin is connected for pulse-skipping mode, the ltc3863 will skip pulses during light loads. in this mode, icmp may remain tripped for several cycles and force the external mosfet to stay off, thereby skipping pulses. this mode offers the benefits of smaller output ripple, lower audible noise, and reduced rf interference, at the expense of lower efficiency when compared to burst mode operation. frequency selection and clock synchronization the switching frequency of the ltc3863 can be selected using the freq pin. if the pllin/mode pin is not being driven by an external clock source, the freq pin can be tied to signal ground, floated, or programmed through an external resistor. tying freq to signal ground selects 350khz, while floating selects 535khz. placing a resistor between freq and signal ground allows the frequency to be programmed between 50khz and 850khz. the phase-locked loop (pll) on the ltc3863 will syn - chronize the internal oscillator to an external clock source when connected to the pllin/mode pin. the pll forces the turn-on edge of the external p-channel mosfet to be aligned with the rising edge of the synchronizing signal.
ltc3863 12 3863f for more information www.linear.com/3863 operation the oscillators default frequency is based on the operating frequency set by the freq pin. if the oscillators default frequency is near the external clock frequency, only slight adjustments are needed for the pll to synchronize the external p-channel mosfets turn-on edge to the rising edge of the external clock. this allows the pll to lock rapidly without deviating far from the desired frequency. the pll is guaranteed from 75khz to 750khz. the clock input levels should be greater than 2v for hi and less than 0.5v for lo. fault protection when the v fb voltage is above +10% of the regulated voltage of 0.8v, this is considered as an overvoltage con - dition and the external p-mosfet is immediately turned off and prevented from ever turning on until v fb returns below +7.5%. in the event of an output short circuit or overcurrent con - dition that causes the output voltage to drop significantly while in current limit, the ltc3863 operating frequency will fold back. anytime the output feedback v fb voltage is less than 50% of the 0.8v internal reference (i.e., 0.4v), frequency foldback is active. the frequency will continue to drop as v fb drops until reaching a minimum foldback frequency of about 18% of the setpoint frequency. fre - quency foldback is designed, in combination with peak current limit, to limit current in start-up and short-circuit conditions. setting the foldback frequency as a percentage of operating frequency assures that start-up characteristics scale appropriately with operating frequency.
ltc3863 13 3863f for more information www.linear.com/3863 the ltc3863 is a nonsynchronous inverting, current mode, constant frequency pwm controller. it drives an external p-channel power mosfet which connects to a schottky power diode acting as the commutating catch diode. the input range extends from 3.5v to 60v. the output range has no theoretical minimum or maximum, but the duty factor and external components practically limit the out - put to one-tenth and ten times the input voltage. higher output ratios can be obtained with transformers and more efficient external components. the ltc3863 offers a highly efficient burst mode operation with 70a quiescent current, which delivers outstanding efficiency in light load operation. the ltc3863 is a low pin count, robust and easy-to-use inverting power supply solution in applications which require high efficiency and operate with widely varying input and output voltages. the typical application on the front page is a basic ltc3863 application circuit. the ltc3863 can sense the inductor current through a high side series sense resistor, r sense , placed between v in and the source of the external p-channel mosfet. once the required output voltage and operating frequency have been determined, external component selection is driven by load requirements, and begins with the selection of inductor and r sense . next, the power mosfet and catch diode are selected. finally, input and output capacitors are selected. output voltage programming the output voltage is programmed by connecting a feedback resistor divider from the output to the v fb pin as shown in figure 1. the output voltage in steady-state operation is set by the feedback resistors according to the equation: v out = ?0.8v ? r fb1 r fb2 applications information great care should be taken to route the v fb and v fbn lines away from noise sources, such as the inductor or sw node or the gate signal that drives the external p- channel mosfet. the integrator capacitor, c fb2 , should be sized to ensure the negative sense amplifier gain rolls off and limits high frequency gain peaking in the dc/dc control loop. the integrator capacitor pole can be safely set to be two times the switching frequency without affecting the dc/dc phase margin according to the following equation. it is highly recommended that c fb2 be used in most applications. c fb2 = 1 2 ? ? 2 ? freq sw switching frequency and clock synchronization the choice of operating frequency is a trade-off between efficiency and component size. lowering the operating fre - quency improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. conversely, raising the operating frequency degrades efficiency but reduces component size. ltc3863 v fb v fbn v out r fb2 c fb2 r fb1 3863 f01 figure 1. setting the output voltage
ltc3863 14 3863f for more information www.linear.com/3863 applications information the ltc3863 can free-run at a user programmed switch - ing frequency, or it can synchronize with an external clock to run at the clock frequency. when the ltc3863 is synchronized, the gate pin will synchronize in phase with the rising edge of the applied clock in order to turn the external p-channel mosfet on. the switching frequency of the ltc3863 is programmed with the freq pin, and the external clock is applied at the pllin/mode pin. table 1 highlights the different states in which the freq pin can be used in conjunction with the pllin/mode pin. table 1 freq pin pllin/mode pin frequency ov dc voltage 350khz floating dc voltage 535khz resistor to gnd dc voltage 50khz to 850khz either of the above external clock phase locked to external clock the free-running switching frequency can be programmed from 50khz to 850khz by connecting a resistor from freq to signal ground. the resulting switching frequency as a function of resistance on the freq pin is shown in figure 2. set the free-running frequency to the desired synchroni - zation frequency using the freq pin so that the internal oscillator is prebiased approximately to the synchronization frequency. while it is not required that the free-running frequency be near the external clock frequency, doing so will minimize synchronization time. inductor selection operating frequency, inductor selection, capacitor selection and efficiency are interrelated. higher operating frequen - cies allow the use of smaller inductors, smaller capacitors, but result in lower efficiency because of higher mosfet gate charge and transition losses. in addition to this basic trade-off, the selection of inductor value is also influenced by other factors. small inductor values result in large inductor ripple cur - rents, large output voltage ripples and low efficiency due to higher core and conduction loss. large inductor ripple currents result in high inductor peak currents, which re - quire physically large inductors with large magnetic cross sections and higher saturation current ratings. the value of the inductor can also impact the stability of the feedback loop. in continuous mode, the buck-boost converter transfer function has a right-half plane zero at a frequency that is inversely proportional to the value of the inductor. as a result, large inductor values can move this zero to a frequency that is low enough to degrade the phase margin of the feedback loop. large inductor values also tend to degrade stability due to low noise margin caused from low ripple current. additionally, large value inductors can lead to slow transient response due to slow inductor current ramping time. for an inverting buck-boost converter operating in con- tinuous conduction mode (ccm), given the desired input, output voltages and switching frequency, the peak-to-peak inductor ripple current is determined by the inductor value: ? i l(ccm) = v in ? d l ? f = v in ? | v out | + v d ( ) l ? f ? v in + | v out | + v d ( ) where v d is the diode forward conduction voltage. in cases where v out >> v d , v d can be ignored. d is the duty factor and is given as: d = | v out | + v d v in + | v out | + v d 0 < d < 1 ( ) figure 2. switching frequency vs resistor on freq freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 3863 f02 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125
ltc3863 15 3863f for more information www.linear.com/3863 applications information the duty factor increases with increasing v out and de- creasing v in . for a given v out , the maximum duty factor occurs at minimum v in . a typical starting point for selecting an inductor is to choose the inductance such that the maximum peak-to-peak in - ductor ripple current, ?i l(max) , is set to 40% ~ 50% of the inductor average current, i l(avg) , at maximum load current. since ? i l(max) occurs at maximum v in in continuous mode, the inductance is calculated at maximum v in : l = v in(max) 2 ? | v out | + v d ( ) 0.4 ? i out(max) ? f ? v in(max) + | v out | + v d ( ) 2 the inductance can be further adjusted to achieve specific design optimization of efficiency, output ripple, component size and loop response. once the inductance value has been determined, the type of inductor must be selected. core loss is independent of core size for a given inductor value, but it is very depen - dent on the inductance selected. as inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore, copper losses will increase. high efficiency converters generally cannot tolerate the core loss of low cost powdered iron cores, forcing the use of more expensive ferrite materials. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on cop - per loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this will result in an abrupt increase in inductor ripple current and output voltage ripple. do not allow the core to saturate! a variety of inductors are available from manufacturers such as sumida, panasonic, coiltronics, coilcraft, toko, vishay, pulse and wrth. current sensing and current limit programming the ltc3863 senses the inductor current through a cur - rent sense resistor, r sense , placed across the v in and sense pins. the voltage across the resistor, v sense , is proportional to inductor current and in normal operation is compared to the peak inductor current setpoint. an inductor current limit condition is detected when v sense exceeds 95mv. when the current limit threshold is exceeded, the p-channel mosfet is immediately turned off by pulling the gate voltage to v in regardless of the controller input. the peak inductor current limit is equal to: i l(peak) ? 95mv r sense ? ? ? ? ? ? this inductor current limit would translate to an output current limit based on the inductor ripple and duty factor: i out(limit) = 95mv r sense ? ? i l 2 ? ? ? ? ? ? ? 1?d ( ) the sense pin is a high impedance input with a maximum leakage of 2a. since the ltc3863 is a peak current mode controller, noise on the sense pin can create pulse width jitter. careful attention must be paid to the layout of r sense . to ensure the integrity of the current sense signal, v sense , the traces from v in and sense pins should be short and run together as a differential pair and kelvin (4-wire) connected across r sense (figure 3). figure 3. inductor current sensing v in r sense ltc3863 v in sense r f mp optional filtering 3863 f03 c f
ltc3863 16 3863f for more information www.linear.com/3863 applications information the ltc3863 has internal filtering of the current sense voltage which should be adequate in most applications. however, adding a provision for an external filter offers added flexibility and noise immunity, should it be neces - sary. the filter can be created by placing a resistor from the r sense resistor to the sense pin and a capacitor across the v in and sense pins. power mosfet selection the ltc3863 drives a p-channel power mosfet that serves as the main switch for the nonsynchronous inverting converter. important p-channel power mosfet parameters include drain-to-source breakdown voltage bv dss , threshold voltage v gs(th) , on-resistance r ds(on) , gate-to-drain reverse transfer capacitance c rss , maximum drain current i d(max) , and the mosfets thermal resistance jc(mosfet) and ja(mosfet) . the drain-to-source breakdown voltage must meet the following condition: bv dss > v in(max) + |v out | + v d the gate driver bias voltage v in -v cap is set by an internal ldo regulator. in normal operation, the cap pin will be regulated to 8v below v in . a minimum 0.1f capacitor is required across the v in and cap pins to ensure ldo stability. if required, additional capacitance can be added to accommodate higher gate currents without voltage droop. in shutdown and burst mode operation, the cap ldo is turned off. in the event of cap leakage to ground, the cap voltage is limited to 9v by a weak internal clamp from v in to cap. as a result, a minimum 10v v gs rated mosfet is required. the power dissipated by the p-channel mosfet when the ltc3863 is in continuous conduction mode is given by: p pmos d ? i out 1?d ? ? ? ? ? ? 2 ? t ? r ds(on) + f ? c miller ? v in + | v out | + v d ( ) 2 2 ? i out 1?d ? r dn v in ? v cap ? v miller ( ) + r up v miller ? ? ? ? ? ? where d is duty factor, r ds(on) is on-resistance of p-channel mosfet, t is temperature coefficient of on- resistance, r dn is the pull-down driver resistance specified at 0.9 typical and r up is the pull-up driver resistance specified at 2 typical. v miller is the miller effective v gs voltage and is taken graphically from the power mosfet data sheet. the power mosfet input capacitance, c miller , is the most important selection criteria for determining the transition loss term in the p-channel mosfet but is not directly speci - fied on mosfet data sheets. c miller is a combination of several components, but it can be derived from the typical gate charge curve included on most data sheets (figure?4). the curve is generated by forcing a constant current out of the gate of a common-source connected p-channel mosfet that is loaded with a resistor, and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and gate-to-drain capacitances. the flat portion of the curve is the result of the miller multipli - cation effect of the drain-to-gate capacitance as the drain figure 4. (4a) typical p-channel mosfet gate charge characteristics and (4b) test set-up to generate gate charge curve s d g v sd(test) r load i gate 3863 f04 miller effect q in (4a) (4b) a b c miller = (q b ? q a )/v sd(test) v sg ? +
ltc3863 17 3863f for more information www.linear.com/3863 applications information voltage rises across the resistor load. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v sd test voltage, but can be adjusted for different v sd voltages by multiplying by the ratio of the adjusted v sd to the curve specified v sd value. a way to estimate the c miller term is to take the change in gate charge from points a and b (or the parameter q gd on a manufacturers data sheet) and dividing it by the specified v sd test voltage, v sd(test) . c miller ? q gd v sd(test) the term with c miller accounts for transition loss, which is highest at high input voltages. for v in < 20v, the high current efficiency generally improves with larger mosfets, while for v in > 20v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. schottky diode selection when the p-channel mosfet is turned off, a power schottky diode is required to function as a commutating diode to carry the inductor current. the average forward diode current is independent of duty factor and is de - scribed as: i f(avg) = i out the worst-case condition for diode conduction is a short- circuit condition where the schottky must handle the maximum current as its duty factor approaches 100% (and the p-channel mosfets duty factor approaches 0%). the diode therefore must be chosen carefully to meet worst- case voltage and current requirements. a good practice is to choose a diode that has a forward current rating two times higher than i out(max) . once the average forward diode current is calculated, the power dissipation can be determined. refer to the schottky diode data sheet for the power dissipation, p diode , as a function of average forward current, i f(avg) . p diode can also be iteratively determined by the two equations below, where v f(iout , tj) is a function of both i f(avg) and junction temperature t j . note that the thermal resistance, ja(diode) , given in the data sheet is typical and can be highly layout dependent. it is therefore important to make sure that the schottky diode has adequate heat sinking. t j ? p diode ? ja(diode) p diode ? i f(avg) ? v d(iout,tj) the schottky diode forward voltage is a function of both i f(avg) and t j , so several iterations may be required to satisfy both equations. the schottky forward voltage, v d , should be taken from the schottky diode data sheet curve showing instantaneous forward voltage. the forward voltage will change as a function of both t j and i f(avg) . the nominal forward voltage will also tend to increase as the reverse breakdown voltage increases. it is therefore advantageous to select a schottky diode appropriate to the input voltage requirements. the diode reverse breakdown voltage must meet the following condition: v r > v in(max) + |v out | c in and c out selection the input and output capacitance, c in /c out , are required to filter the square wave current through the p-channel mosfet and diode respectively. use a low esr capacitor sized to handle the maximum rms current: i cin(rms) = i cout(rms) = i out s | v out | + v d v in
ltc3863 18 3863f for more information www.linear.com/3863 applications information the formula shows that the rms current is greater than the maximum i out when v out is greater than v in . choose capacitors with higher rms rating with sufficient margin. note that ripple current ratings from capacitor manufac - turers are often based on only 2000 hours of life, which makes it advisable to derate the capacitor. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the ?v out is approximately bounded by: ? v out i l(peak) ? esr + i out ? d f ? c out where i l(peak) is the peak inductor current and its given as: i l(peak) = i out v in + | v out | + v d ( ) v in + v in ? | v out | + v d ( ) 2 ? l ? f ? v in + | v out | + v d ( ) since i l(peak) and d reach their maximum values at mini - mum v in , the output voltage ripple is highest at minimum v in and maximum i out . typically, once the esr require - ment is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, specialty polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. specialty polymer capacitors offer very low esr but have lower specific capacitance than other types. tantalum capacitors have the highest specific capacitance, but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long- term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. when used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvolt - age hazard to the power switch and controller. to dampen input voltage transients, add a small 5f to 40f aluminum electrolytic capacitor with an esr in the range of 0.5 to 2. high performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of lead inductance. discontinuous and continuous operation the ltc3863 operates in discontinuous conduction (dcm) until the load current is high enough for the inductor current to be positive at the end of the switching cycle. the output load current at the continuous/discontinuous boundary, i out(cdb) , is given by the following equation: i out(cdb) = v in(max) 2 ? | v out | + v d ( ) 2 ? l ? f ? v in(max) + | v out | + v d ( ) 2 the continuous/discontinuous boundary is inversely proportional to the inductor value. therefore, if required, i out(cdb) can be reduced by increasing the inductor value. external soft-start and output tracking start-up characteristics are controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the internal 0.8v reference, the ltc3863 regulates the v fb pin voltage to the voltage on the ss pin. when the ss pin is greater than the internal 0.8v reference, the v fb pin voltage regulates to the 0.8v internal reference. the ss pin can be used to program an external soft-start function or to allow v out to track another supply during start-up.
ltc3863 19 3863f for more information www.linear.com/3863 figure 5a. two different modes of output tracking figure 5b. setup for ratiometric and coincident tracking time coincident tracking external supply external supply ?v out (v out < 0v) ?v out (v out < 0v) voltage time 3863 f05a ratiometric tracking voltage r1 = r fb1 ? r fb2 |v out | > 0.8v ext. v r2 = r fb2 coincident tracking setup to ss r fb1 v out to v fbn to fb to fb r fb2 r1 ext. v r2 r1+ r2 r2 to ss r fb1 v out to v fbn r fb2 3863 f05b ratiometric tracking setup 0.8v ext. v applications information soft-start is enabled by connecting a capacitor from the ss pin to ground. an internal 10a current source charges the capacitor, providing a linear ramping voltage at the ss pin that causes v out to rise smoothly from 0v to its final regulated value. the total soft-start time will be approximately: t ss = c ss ? 0.8v 10a when the ltc3863 is configured to track another supply, a voltage divider can be used from the tracking supply to the ss pin to scale the ramp rate appropriately. two com - mon implementations of tracking as shown in figure?5a are coincident and ratiometric. for coincident tracking, choose the divider ratio for the external supply as shown in figure 5b. ratiometric tracking could be achieved by using a different ratio than the feedback (figure 5b). note that the soft-start capacitor charging current is always flowing, producing a small offset error. to minimize this error, select the tracking resistive divider values to be small enough to make this offset error negligible. short-circuit faults: current limit and foldback the inductor current limit is inherently set in a current mode controller by the maximum sense voltage and r sense . in the ltc3863, the maximum sense voltage is 95mv, mea - sured across the inductor sense resistor, r sense , placed across the v in and sense pins. the output current limit is approximately: i limit(min) = 95mv r sense ? ? i l 2 ? ? ? ? ? ? ? v in(min) v in(min) + | v out | + v d ( ) the current limit must be chosen to ensure that i limit(min) > i out(max) under all operating conditions. the inductor current limit should be greater than the inductor current required to produce maximum output power at worst-case efficiency. for the ltc3863, both minimum and maximum v in cases should be checked to determine the worst-case efficiency. short-circuit fault protection is assured by the combination of current limit and frequency foldback. when the output feedback voltage, v fb , drops below 0.4v, the operating
ltc3863 20 3863f for more information www.linear.com/3863 applications information frequency, f, will fold back to a minimum value of 0.18???f when v fb reaches 0v. both current limit and frequency foldback are active in all modes of operation. in a short- circuit fault condition, the output current is first limited by current limit and then further reduced by folding back the operating frequency as the short becomes more se- vere. the worst-case fault condition occurs when v out is shorted to ground. short-circuit recovery and internal soft-start an internal soft-start feature guarantees a maximum posi- tive output voltage slew rate in all operational cases. in a short-circuit recovery condition for example, the output recovery rate is limited by the internal soft-start so that output voltage overshoot and excessive inductor current buildup is prevented. the internal soft-start voltage and the external ss pin operate independently. the output will track the lower of the two voltages. the slew rate of the internal soft-start voltage is roughly 1.2v/ms, which translates to a total soft-start time of 650s. if the slew rate of the ss pin is greater than 1.2v/ms the output will track the internal soft- start ramp. to assure robust fault recovery, the internal soft-start feature is active in all operational cases. if a short-circuit condition occurs which causes the output to drop significantly, the internal soft-start will assure a soft recovery when the fault condition is removed. the internal soft-start assures a clean soft ramp-up from any fault condition that causes the output to droop, guar - anteeing a maximum ramp rate in soft-start, short-circuit fault release. figure 6 illustrates how internal soft-start controls the output ramp-up rate under varying scenarios. v in undervoltage lockout (uvlo) the ltc3863 is designed to accommodate applications requiring widely varying power input voltages from 3.5v to 60v. to accommodate the cases where v in drops sig - nificantly once in regulation, the ltc3863 is guaranteed to operate down to a v in of 3.5v over the full temperature range. the implications of both the uvlo rising and uvlo falling specifications must be carefully considered for low v in operation. the uvlo threshold with v in rising is typi - cally 3.5v (with a maximum of 3.8v) and uvlo falling is typically 3.25v (with a maximum of 3.5v). the operating input voltage range of the ltc3863 is guaranteed to be 3.5v to 60v over temperature, but the initial v in ramp must exceed 3.8v to guarantee start-up. minimum on-time considerations the minimum on-time, t on(min) , is the smallest time duration that the ltc3863 is capable of turning on the power mosfet, and is typically 220ns. it is determined by internal timing delays and the gate charge required to turn on the mosfet. low duty cycle applications may approach this minimum on-time limit, so care should be taken to ensure that: t on(min) < | v out | + v d ( ) f s v in(max) + | v out | + v d ( ) figure 6. internal soft-start (6a) allows soft-start without an external soft-start capacitor and allows soft recovery from (6b) a short-circuit time ~650s (6a) ??v out v in voltage 3863 f06 internal soft-start induced start-up (no external soft-start capacitor) time short-circuit (6b) ?v out voltage internal soft-start induced recovery
ltc3863 21 3863f for more information www.linear.com/3863 applications information if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will skip cycles. however, the output voltage will continue to regulate. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine the dominant contributors and therefore where efficiency improvements can be made. percent efficiency can be expressed as: % efficiency = 100% - (l1+l2+l3+) where l1, l2, l3, etc., are the individual losses as a per - centage of input power. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in ltc3863 application circuits. 1. conduction loss: conduction losses result from the p-channel mosfet r ds(on) , inductor resistance dcr, the current sense resistor r sense , and input and output capacitor esr. the current through dcr is continuous. the currents through both the p-channel mosfet and schottky diode are discontinuous. the following equa - tion may be used to determine the total conduction loss (p cond ) in continuous conduction mode: p cond i out 2 1?d ( ) 2 + ? i l 2 12 ? ? ? ? ? ? ? r dcr + d ? r ds(on) + r sense + r esr(cin) ( ) + 1?d ( ) ? r esr(cout) ? ? ? ? ? ? ? ? 2. transition loss: transition loss of the p-channel mosfet becomes significant only when operating at high input voltages (typically 20v or greater.) the p - channel transition losses (p mostrl ) can be deter - mined from the following equation: p pmostrl = f ? c miller ? v in + | v out | + v d ( ) 2 2 ? i out 1?d ? r dn v in ? v cap ( ) ? v miller + r up v miller ? ? ? ? ? ? 3. gate charging loss: charging and discharging the gate of the mosfet will result in an effective gate charg - ing current. each time the p-channel mosfet gate is switched from low to high and low again, a packet of charge, dq, moves from the capacitor across v in C v cap and is then replenished from ground by the internal v cap regulator. the resulting dq/dt current is a current out of v in flowing to ground. the total power loss in the controller including gate charging loss is determined by the following equation: p cntrl = v in t* q gt2 g(pmosfet) ) 4. schottky loss: the schottky loss is independent of duty factors. the critical component is the schottky forward voltage as a function of junction temperature and current. the schottky power loss is given by the equation: p diode = i out t7 d(iout,tj) when making adjustments to improve efficiency, the in - put current is the best indicator of changes in efficiency. if changes cause the input current to decrease, then the efficiency has increased. if there is no change in input current, there is no change in efficiency.
ltc3863 22 3863f for more information www.linear.com/3863 applications information opti-loop ? compensation opti-loop compensation, through the availability of the ith pin, allows the transient response to be optimized for a wide range of loads and output capacitors. the ith pin not only allows optimization of the control loop behavior but also provides a test point for the regulator s dc-coupled and ac-filtered closed-loop response. the dc step, rise time and settling at this test point truly reflects the closed- loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at this pin. the ith series r ith -c ith1 filter sets the dominant pole-zero loop compensation. additionally, a small capacitor placed from the ith pin to signal ground, c ith2 , may be required to attenuate high frequency noise. the values can be modified to optimize transient response once the final pcb layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because their various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the general goal of opti-loop compensation is to realize a fast but stable ith response with minimal output droop due to the load step. for a detailed explanation of opti-loop compensation, refer to application note 76. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out im - mediately shifts by an amount equal to ? i load ? esr, where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out , generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. connecting a resistive load in series with a power mosfet, then placing the two directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load-step condi - tion. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated feedback loop response. the gain of the loop increases with r ith and the bandwidth of the loop increases with decreasing c ith1 . if r ith is increased by the same factor that c ith1 is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. in addition, a feedforward capacitor, c ff , can be added to improve the high frequency response, as shown in figure 1. capacitor c ff provides phase lead by creating a high frequency zero with r b1 which improves the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate overall performance of the regulator. in some applications, a more severe transient can be caused by switching in loads with large (>10f) input capacitors. if the switch connecting the load has low resistance and is driven quickly, then the discharged input capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed specifically for this purpose and usually incorporates cur - rent limiting, short-circuit protection and soft-start. large-signal effects on ith inverting controllers have a wide range of applications and operating conditions which affect compensation. low switching frequencies and the inverting buck-boost right-half-plane zero can result in very low gain crossover frequency requirements. low crossover frequencies often require a compensation r ith and c ith that are too small for
ltc3863 23 3863f for more information www.linear.com/3863 applications information the error amplifier output drive current on ith of 100a. the effect causes ith to appear clamped in response to a transient load current step which causes excessive output droop. an r ith greater than 20k allows ith to swing 1.5v with margin for temperature and part to part variation and should never have this issue. in applications with less severe transient load step requirements, r ith can safely be set as low as 10k. we do not recommend less than 10k in any application. if r ith is too small then either the operating frequency will need to be increased or the output capacitor increased to increase the r ith required to stabilize the system. we strongly recommend that any system with an r ith less than 20k be experimentally veri - fied with worst-case load steps. design example consider an inverting converter with the following speci - fications: v in = 4.5v to 55v, v out = C5v, i out(max) = 1.8a, and f = 320khz (figure 7). the output voltage is programmed according to: v out = ?0.8v ? r fb2 r fb1 if r fb2 is chosen to be 188k, then r fb1 needs to be 30.1k. the freq pin is tied to signal ground in order to program the switching frequency to 350khz. the on-time required to generate C5v output from 55v v in in continuous mode can be calculated as: t on(ccm) = 5v + 0.5v 320khz ? 55v + 5v + 0.5v ( ) = 260ns this on-time, t on , is larger than ltc3863s minimum on- time with sufficient margin to prevent cycle skipping. use a lower frequency if a larger on-time margin is needed to account for variations from minimum on-time and switch - ing frequency. as load current decreases, the converter will eventually start cycle skipping. next, set the inductor value such that the inductor ripple current is 60% of the average inductor current at maximum v in = 55v and full load = 1.8a: l = 55v 2 ? 5v + 0.5v ( ) 0.6 ? 1.8a ? 320khz ? 55v + 5v + 0.5v ( ) 2 13.1h select a standard value of 12h. the resulting ripple current at minimum v in of 4.5v is: ? i l = 5v ? 5v + 0.5v ( ) 12h ? 320khz ? 5v + 5v + 0.5v ( ) = 0.644a figure 7. design example (4.5v to 55v input, C5v, 1.8a at 320khz) 320khz 16m l1 12h q1 d1 cap 0.47f pgnd ltc3863 3863 f07 ss ith freq sgnd run v in pllin/mode sense gate v fbn v fb 10k 52.3k 187k c out3 100f 20v v out ?5v 1.8a 30.1k c in1 : cde afk686m63g24t-f c in2 : tdk cga6m3x7s2a475k c out1 : tdk c4532x7r1c336m c out3 : panasonic 20svp100m d1: vishay ss8ph9-m3/87a l1: mss1278-123ml q1: vishay si7469dp v in 4.5v to 55v c in1 68f 63v c in2 4.7f 100v 2 15nf 220pf 0.1f c out1 33f 16v 2 12pf + +
ltc3863 24 3863f for more information www.linear.com/3863 applications information the boundary output current for continuous/discontinuous mode is calculated: i out(cdb) = 55v 2 ? 5v 2 ? 12h ? 320khz ? 55v + 5v ( ) 2 = 0.55a the maximum inductor peak current occurs at minimum v in of 4.5v and full load of 1.8a where ltc3863 operates in continuous mode is: i l(peak _ max) = 1.8a ? 4.5v + 5v + 0.5v ( ) 5v + ? i l 2 = 3.6a + 0.644a 2 4.25a next, set the r sense resistor value to ensure that the converter can deliver the maximum peak inductor current of 4.25a with sufficient margin to account for component variations and worst-case operating conditions. using a 30% margin factor: r sense = 95mv 1.3 ? 4.25a = 17.2m ? use a more readily available 16m sense resistor. this results in peak inductor current limit: i l(peak) = 95mv 16m ? = 5.94a choose an inductor that has rated saturation current higher than 5.94a with sufficient margin. the output current limit can be calculated from the peak inductor current limit and its minimum occurs at minimum v in of 5v: i limit(min) = 95mv 16m ? ? 0.644a 2 ? ? ? ? ? ? ? 5v 4.5v + 5v + 0.5v ( ) = 2.8a in this example, 2.8a is the maximum output current the switching regulator can support at v in = 4.5v. it is larger than the full load of 1.8a by a margin of 1a. if a larger margin is needed, use a smaller r sense . next choose a p-channel mosfet with the appropriate bv dss and i d rating. the bv dss rating should be greater than (55v + 5v + v d ) with sufficient margin. in this ex - ample, a good choice is the vishay si7469dp (bv dss = 80v, i d = 10a, r ds(on) = 30m, 100c = 1.8, v miller = 3.2v, c miller = 235pf, ja = 24c/w). the highest power dissipation and the resulting junction temperature for the p-channel mosfet occurs at the minimum v in of 5v and maximum output current of 1.8a. they can be calculated at t a = 70c as follows: d = 5v + 0.5v 4.5v + 5v + 0.5v 0.55 p pmos = 0.55 ? 1.8a 1? 0.55 ? ? ? ? ? ? 2 ? 1.8 ? 30m ? + 320khz ? 235pf ? 4.5v + | ?5v| + 0.5v ( ) 2 2 ? 1.8a 1? 0.55 ( ) ? 0.9 ? 4.5v ? 3.2v + 2 ? 3.2v ? ? ? ? ? ? 0.475w + 0.020w 0.495w t j ??8t8? the same calculations can be repeated for v in(max) = 55v: d = 5v + 0.5v 55v + 5v + 0.5v 0.091 p pmos 0.091 ? 1.8a 1? 0.091 ? ? ? ? ? ? 2 ? 1.8 ? 30m ? + 320khz ? 235pf ? 55v + | ?5v| + 0.5v ( ) 2 2 ? 1.8a 1? 0.091 ( ) ? 0.9 ? 5v ? 3.2v + 2 ? 3.2v ? ? ? ? ? ? 0.019w + 0.39w 0.411w t j ?8t8? next choose an appropriate schottky diode that will handle the power requirements. the reverse voltage of the diode, v r , should be greater than (55v + 5v). the fairchild s38 schottky diode is selected (v f (3a,125c) = 0.45v,
ltc3863 25 3863f for more information www.linear.com/3863 v r = 80v, ja = 55c/w) for this application. the power dissipation and junction temperature at t a = 70 and full load = 1.8a can be calculated as: p diode = 1.8a ? 0.45v = 0.81w t j = 70c + 0.81w ? 55c/w = 114c these power dissipation calculations show that careful attention to heat sinking will be necessary. for the input bypass capacitors, choose low esr ceramic capacitors that can handle the maximum rms current at the minimum v in of 4.5v: i cin(rms) 1.8a s | ?5v| 4.5v = 1.9a c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement. for this design, two 47f ceramic capacitors are chosen to offer low ripple in both normal operation and in burst mode operation. the selected c out must support the maximum rms operating current at a minimum v in of 4.5v: i cin(rms) 1.8a s | ?5v| 4.5v = 1.9a a soft-start time of 8ms can be programmed through a 0.1f capacitor on the ss pin: c ss = 8ms s 10a 0.8v = 0.1f loop compensation components on the ith pin are chosen based on load step transient behavior (as described under opti-loop compensation) and is optimized for stability. a pull-up resistor is used on the run pin for fmea compli - ance (see failure modes and effects analysis). an application with complementary dual outputs of 5v can be designed by using two ltc3863 parts with one configured into an inverting regulator and the other into a step-down buck regulator as shown in figure?11. refer to ltc3864 data sheet for the actual design of a buck output of 5v. gate driver component placement, layout and routing it is important to follow recommended power supply pc board layout practices such as placing external power ele - ments to minimize loop area and inductance in switching paths. be careful to pay particular attention to gate driver component placement, layout and routing. the effective c cap capacitance should be greater than 0.1f minimum in all operating conditions. operating voltage and temperature both decrease the rated capacitance to varying degrees depending on dielectric type. the ltc3863 is a pmos controller with an internal gate driver and boot- strapped ldo that regulates the differential cap voltage (v in C v cap ) to 8v nominal. the c cap capacitance needs to be large enough to assure stability and provide cycle- to-cycle current to the pmos switch with minimum series inductance. we recommend a ceramic 0.47f 16v capacitor with a high quality dielectric such as x5r or x7r. some high current applications with large qg pmos switches may benefit from an even larger c cap capacitance. figure 8 shows the ltc3863 generic application sche - matic which includes an optional current sense filter and series gate resistor. figure 9 illustrates the recommended gate driver component placement, layout and routing of the gate, v in , sense and cap pins and key gate driver components. it is recommended that the gate driver layout follow the example shown in figure 9 to assure proper operation and long term reliability. the ltc3863 gate driver should connect to the external power elements in the following manner. first route the v in pin using a single low impedance isolated trace to the positive r sense resistor pad without connection to the v in plane. the reason for this precaution is that the v in pin is internally kelvin connected to the current sense comparator, internal v in power and the pmos gate driver. connecting the v in pin to the v in power plane adds noise and can result in jitter or instability. figure 9 shows a single v in trace from the positive r sense pad connected to c sf , c cap , v in pad and c inb . the total trace length to r sense should be minimized and the capacitors c cf , c cap and c inb should be placed near the v in pin of the ltc3863. applications information
ltc3863 26 3863f for more information www.linear.com/3863 applications information c cap should be placed near the v in and cap pins. figure 9 shows c cap placed adjacent to the v in and cap pins with sense routed between the pads. this is the recommended layout and results in the minimum parasitic inductance. the gate driver is capable of providing high peak current. parasitic inductance in the gate drive and the series in - ductance between v in to cap can cause a voltage spike between v in and cap on each switching cycle. the voltage spike can result in electrical over-stress to the gate driver and can result in gate driver failures in extreme cases. it is recommended to follow the example shown in figure 9 for the placement of c cap as close as is practical. c sf l1 q1 d1 cap c cap pgnd ltc3863 3863 f08 ss ith freq sgnd ground plane to pgnd run v in pllin/mode sense gate v fbn v fb r ith r sf r sense r gate r freq r fb1 r fb2 v out v in c in + ? c ith c pith c inb c ss c out c fb2 figure 8: ltc3863 generic application schematic with optional current sense filter and series gate resistor r gate to q1 gate to r sense + 3863 f09 c inb c cap gate sense cap v in c sf r sf to r sense ? figure 9: ltc3863 recommended gate driver pc board placement, layout and routing r gate resistor pads can be added with a 0 resistor to allow the damping resistor to be added later. the total length of the gate drive trace to the pmos gate should be minimized and ideally be less than 1cm. in most cases with a good layout the r gate resistor is not needed. the r gate resistor should be located near the gate pin to re - duce peak current through gate and minimize reflected noise on the gate pin. the r sf and c sf pads can be added with a zero ohm resis - tor for r sf and c sf not populated. in most applications, external filtering is not needed. the current sense filter r sf and c sf can be added later if noise if demonstrated to be a problem. the bypass capacitor c inb is used to locally filter the v in supply. c inb should be tied to the v in pin trace and to the pgnd exposed pad. the c inb positive pad should connect to r sense positive though the v in pin trace. the c inb ground trace should connect to the pgnd exposed pad connection. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3863. 1. multilayer boards with dedicated ground layers are preferable for reduced noise and for heat sinking pur - poses. use wide rails and/or entire planes for v in , v out and gnd for good filtering and minimal copper loss. if a ground layer is used, then it should be immediately below (and/or above) the routing layer for the power train components which consist of c in , sense resistor, p-channel mosfet, schottky diode, inductor, and c out . flood unused areas of all layers with copper for better heat sinking. 2. keep signal and power grounds separate except at the point where they are shorted together. short the signal and power ground together only at a single point with a narrow pcb trace (or single via in a multilayer board). all power train components should be referenced to power ground and all small-signal components (e.g., c ith1 , r freq , c ss etc.) should be referenced to the signal ground.
ltc3863 27 3863f for more information www.linear.com/3863 c z 2n3904 ss r z v z ?v out 3863 f10 figure 10 applications information 3. place c in , sense resistor, p-channel mosfet, induc - tor, and primary c out capacitors close together in one compact area. the junction connecting the drain of the p - channel mosfet, cathode of the schottky, and (+) terminal of the inductor (this junction is com - monly referred to as switch or phase node) should be compact but be large enough to handle the inductor currents without large copper losses. place the sense resistor and source of p-channel mosfet as close as possible to the (+) plate of the c in capacitor(s) that provides the bulk of the ac current (these are normally the ceramic capacitors), and connect the (C) terminal of the inductor as close as possible to the (C) terminal of the same c in capacitor(s). the high di/dt loop formed by c in , the mosfet, and the schottky diode should have short leads and pcb trace lengths to minimize high frequency emi and voltage stress from inductive ringing. the (+) terminal of the primary c out capacitor(s) which filter the bulk of the inductor ripple current (these are normally the ceramic capacitors) should also be connected close to the (C) terminal of c in . 4. place pins 7 to 12 facing the power train components. keep high dv/dt signals on gate and switch away from sensitive small-signal traces and components. 5. place the sense resistor close to the (+) terminal of c in and source of p-channel mosfet. use a kelvin (4-wire) connection across the sense resistor and route the traces together as a differential pair into the v in and sense pins. an optional rc filter could be placed near the v in and sense pins to filter the current sense signal. 6. place the resistive feedback divider r fb1/2 as close as possible to the v fb and v fbn pins. the (C) terminal of the feedback divider should connect to the output regulation point and the (+) terminal of the feedback divider should connect to v fb . 7. place the ceramic c cap capacitor as close as possible to the v in and cap pins. this capacitor provides the gate discharging current for the power p-channel mosfet. 8. place small signal components as close to their respective pins as possible. this minimizes the possibility of pcb noise coupling into these pins. give priority to v fb , ith, and r freq pins. use sufficient isolation when routing a clock signal into the pllin /mode pin so that the clock does not couple into sensitive small-signal pins. failure mode and effects analysis (fmea) a fmea study on the ltc3863 has been conducted through adjacent pin opens and shorts. the device was tested in a step-down application (figure 15) from v in = 12v to v out = C5v with a current load of 2a on the output. one group of tests involved the application being monitored while each pin was disconnected from the pc board and left open while all other pins remained intact. the other group of tests involved each pin being shorted to its adjacent pins while all other pins were connected as it would be normally in the application. the results are shown in table 2. for fmea compliance, the following design implementa - tions are recommended: ? if the run pin is being pulled up to a voltage greater than 6v, then it is done so through a pull-up resistor (100k to 1m) so that the v fbn pin is not damaged in case of a run to v fbn short. ? the gate of the external p-channel mosfet should be pulled through a resistor (20k to 100k) to the input supply, v in so that the p-channel mosfet is guaranteed to turn off in case of a gate open. ? to protect against the v fbn open condition it is neces - sary to add an output shutdown clamp. the output shutdown clamp is comprised of a zener, v z , npn and zener bias resistor, r z , to ground as found in figure?10. the clamp voltage will be the zener forward voltage v z plus a v be . the clamp needs to be designed such that the worst-case minimum zener voltage is less than the maximum operating voltage. the worst-case zener leakage current times the zener bias resistor should not exceed 200mv.
ltc3863 28 3863f for more information www.linear.com/3863 applications information table 2 failure mode v out i out i vin f recovery when fault is removed? behavior none C5v 1a 453ma 350khz n/a normal operation. pin open open pin 1 (pllin/mode) C5v 1a 453ma 350khz ok pin already left open in normal application, so no difference. open pin 2 (freq) C5v 1a 453ma 535khz ok frequency jumps to default open value. open pin 3 (gnd) C5v 1a 453ma 350khz ok exposed pad still provides gnd connection to device. open pin 4 (ss) C5v 1a 453ma 350khz ok external soft-start removed, but internal soft-start still available. open pin 5 (v fb ) 0v 0a 0.7ma 0khz ok controller stops switching. v fb internally self biases hi to prevent switching. open pin 6 (ith) C5v 1a 507ma 40khz ok output still regulating, but the switching is erratic. loop not stable. open pin 7 (v fbn ) C6v pk 1a 502ma 350khz ok use a 5.1v zener v z , 10k r z and 0.01f c z . output voltage is C6v peak and averages C4.9v. open pin 8 (run) C5v 1a 453ma 350khz ok controller does not start-up. open pin 9 (cap) C5v 1a 453ma 350khz ok more jitter during switching, but regulates normally. open pin 10 (sense) 0v 0a 0.7ma 0khz ok sense internally prebiases to 0.6v below v in . this prevents controller from switching. open pin 11 ( v in ) C5.4v 1a 597ma 20khz ok v in able to bias internally through sense. regulates with high v out ripple. open pin 12 ( gate) 0v 0a 0.7ma 0khz ok gate does not drive external power fet, preventing output regulation. open pin 13 (pgnd) C5v 453ma 350khz ok pin 3 (gnd) still provides gnd connection to device. pins shorted short pins 1, 2 (pllin/mode and freq) C5v 1a 453ma 350khz ok burst mode operation disabled, but runs normally as in pulse- skipping mode. short pins 2, 3 (freq and gnd) C5v 1a 453ma 0khz ok freq already shorted to gnd, so regulates normally. short pins 3, 4 (gnd and ss) 0v 0a 0.7ma 0khz ok ss short to gnd prevents device from starting up. short pins 4, 5 (ss and v fb ) C1v(dc) C3v p-p 50ma 9ma erratic ok v out oscillates from 0v to 3v. short pins 5, 6 (v fb and ith) C3.15v 625ma 181ma 350khz ok controller loop does not regulate to proper output voltage. short pins 7, 8 (v fbn and run) 5v 0a 860a 350khz ok controller does not start-up. short pins 8, 9 (run and cap) C5v 1a 453ma 350khz ok able to start-up and regulate normally. short pins 9, 10 (cap and sense) 0v 0a 181ma 0khz ok cap ~ v in , which prevents turning on external p-mosfet. short pins 10, 11 (sense and v in ) C5v 1a 453ma 50khz ok regulates with high v out ripple. short pins 11, 12 (v in and gate) 0v 0a 29ma 0khz ok power mosfet is always kept off, preventing regulation.
ltc3863 29 3863f for more information www.linear.com/3863 figure 11. design example, 4.5v to 55v input, 5v, 1.8a at 320khz positive 5v efficiency negative 5v efficiency positive 5v gain/phase negative 5v gain/phase typical applications 16m l1 12h q1 d1 cap 0.47f pgnd ltc3863 3863 f11a ss ith freq sgnd run v in pllin/mode sense gate v fbn v fb 10k 52.3k 187k c out3 100f 20v v out ?5v 1.8a 30.1k d2: diodes sbr3u100lp-7 l2: toko b1134as-100m q2: fairchild fdmc5614p c out4 : tdk c4532x5r0j07m c out5 : panasonic eee-fk1v221p c in1 : cde afk686m63g24t-f c in2 : tdk cga6m3x7s2a475k c out1 tdk c4532x7r1c336m c out3 panasonic 20svp100m d1: vishay ss8ph9-m3/87a l1: mss1278-123ml q1: vishay si7469dp v in * 4.5v to 55v c in1 68f 63v c in2 4.7f 100v 2 15nf 220pf 0.1f 0.1f 0.1f c out1 33f 16v 2 12pf 25m l2 10h q2 d2 cap 0.47f pgnd ltc3864 ss ith freq sgnd run v in pllin/mode sense gate pgood v fb 15k 52.3k c out5 220f 35v c out4 100f 6.3v *v out follows v in when 3.5v < v in < 5.2v note: ltc3863 can be used in place of ltc3864 if v fbn is tied > 2v v out * 5v 1.8a 10nf 220pf 422k 80.6k ltc6908-1 v + sync1 gnd sync2 set mod 320khz 316k + + + gain/phase measurements taken with omicron lab bode 100 vector network analyzer. load current (a) 0.002 40 efficiency (%) power loss (w) 50 60 70 80 0.02 0.2 2 3863 f11b 30 20 10 0 90 100 4 5 6 7 8 3 2 1 0 9 10 efficiency power loss v in = 12v v out = 5v pulse-skipping mode burst mode operation frequency (khz) 1 ?30 gain (db) phase (deg) ?10 10 30 50 10 100 3863 f11c 70 ?20 0 20 40 60 ?45 ?15 15 0 45 75 105 ?30 phase gain 30 60 90 load current (a) 0.002 40 efficiency (%) power loss (w) 60 90 80 0.02 0.2 2 3863 f11d 20 30 50 70 10 0 4 6 9 8 2 3 5 7 1 0 efficiency power loss v in = 12v v out = ?5v pulse-skipping mode burst mode operation frequency (khz) 1 ?30 gain (db) phase (deg) ?20 ?10 0 10 20 30 40 50 10 100 3863 f11e 60 ?45 ?30 ?15 0 15 30 45 60 75 90 phase gain
ltc3863 30 3863f for more information www.linear.com/3863 typical applications figure 12. 5v to 23v input, C18v/700ma output, 750khz inverting converter efficiency gain/phase gain/phase measurements taken with omicron lab bode 100 vector network analyzer. 750khz 25m l1 15h q1 d1 cap 0.47f pgnd ltc3863 3863 f12a ss ith freq sgnd run v in pllin/mode sense gate v fbn v fb 36.5k 100k 191k v out ?18v 700ma 8.45k c in1 : nichicon ucj1h101mcl1gs c in2 : tdk c3225x7r1e108m c out1 : murata grm32dr61e106ka12l c out3 : panasonic 20svo100m d1: diodes sbr8u60p5 l1: wurth 744770115 q1: vishay si7469dp v in 5v to 23v c in2 10f 25v 2 c out1 10f 25v 2 c in1 100f 50v c out3 100f 20v 4.7nf 0.1f 50pf 47pf + + load current (a) 0.001 40 efficiency (%) power loss (w) 60 90 80 0.01 0.1 1 3863 f12b 20 30 50 70 10 0 4 6 9 8 2 3 5 7 1 0 efficiency power loss v in = 12v v out = ?18v pulse-skipping mode burst mode operation frequency (khz) 1 ?30 gain (db) phase (deg) ?20 ?10 0 10 20 30 40 50 10 100 3863 f12c 60 ?45 ?30 ?15 0 15 30 45 60 75 90 phase gain v in = 12v v out = ?18v
ltc3863 31 3863f for more information www.linear.com/3863 typical applications figure 13. 3.5v to 28v input, C0.4v/200ma output, 80khz inverting converter efficiency gain/phase gain/phase measurements taken with omicron lab bode 100 vector network analyzer. 80khz 82m l1 15h q1 d1 cap 0.47f pgnd ltc3863 3863 f13a ss ith freq sgnd run v in pllin/mode sense gate v fbn v fb 5k 61.9k 95.3k v out ?0.4v 200ma 191k c in1 : nichicon ucj1h101mcl1gs c in2 : murata grm32er71h108h c out1 : tdk c4532x7r1c336m c out3 : panasonic 16tqc150myf d1: diodes b540c-13-f l1: wurth 7447779115 q1: fairchild fdmc5614p v in 3.5v to 28v c in1 100f 50v c out1 10f 25v 2 c in2 10f 50v 2 c out3 100f 20v 3.3nf 0.1f 82pf 10pf + + load current (a) efficiency (%) power loss (w) 50 40 30 3863 f13b 0 20 10 0.5 0.4 0.3 0 0.2 0.1 0.2 0.002 0.02 efficiency power loss v in = 12v v out = ?0.4v pulse-skipping mode burst mode operation frequency (khz) 1 ?30 gain (db) phase (deg) ?20 ?10 0 10 20 30 40 50 10 100 3863 f13c 60 ?45 ?30 ?15 0 15 30 45 60 75 90 phase gain v in = 12v v out = ?0.4v
ltc3863 32 3863f for more information www.linear.com/3863 typical applications efficiency gain/phase figure 14. 12v to 42v input, C48v/300ma output, 440khz inverting converter gain/phase measurements taken with omicron lab bode 100 vector network analyzer. 440khz 27m l1 10h q1 d1 cap 0.47f pgnd ltc3863 3863 f14a ss ith freq sgnd run v in pllin/mode sense gate v fbn v fb 1m 64.9k 196k v out ?48v 300ma 3.32k c in1 : nichicon ucj1h101mcl1gs c in2 : murata grm32er71h106h c out1 : tdk cga6m3x7s2a475k c out3 : ucc emvh630ara101mke d1: diodes pds5100h l1: wurth 744314101 q1: vishay si7113dn v in 12v to 42v c in1 100f 50v c out1 4.7f 100v 2 c in2 10f 50v 2 c out3 100f 63v 18nf 0.1f 100pf + + load current (a) 0.001 40 efficiency (%) power loss (w) 60 90 80 0.01 0.1 3863 f14b 20 30 50 70 10 0 4 6 9 8 2 3 5 7 1 0 efficiency power loss v in = 24v v out = ?48v pulse-skipping mode burst mode operation frequency (khz) 2 ?30 gain (db) phase (deg) ?10 10 30 50 20 200 3863 f14c 70 ?20 0 20 40 60 ?45 ?15 15 0 45 75 105 ?30 phase gain 30 60 90 v in = 24v v out = ?48v
ltc3863 33 3863f for more information www.linear.com/3863 figure 15. 4.5v to 16v input, C5v/1.7a, C12v/1a output, 350khz inverting converter typical applications 350khz 16m l1 10h q1 d1 cap 0.47f pgnd ltc3863 3863 f15a ss ith freq sgnd run v in pllin/mode sense gate v fbn v fb 14.7k 61.9k r fbo 698k v out ?5v 1.7a (short r fbo ) ?12v 1a 80.6k c in1 : panasonic 20svp100m c in2 : tdk c3225x7r1e106m c out1 : tdk c4532x7r1c336m c out3 : panasonic 16tqc150myf d1: diodes b540c l1: toko 919as-100m q1: vishay si7129dn-t1-ge3 v in 4.5v to 16v c in1 100f 20v c out1 33f 16v 2 c in2 10f 25v 2 c out3 150f 16v 2 27nf 0.1f 390pf 68pf 511k + + C5v efficiency C12v efficiency load current (a) 0.002 40 efficiency (%) power loss (w) 60 90 80 0.02 0.2 2 3863 f15b 20 30 50 70 10 0 4 6 9 8 2 3 5 7 1 0 efficiency power loss v in = 12v v out = ?5v pulse-skipping mode burst mode operation load current (a) 0.002 40 efficiency (%) power loss (w) 60 90 80 0.02 0.2 2 3863 f15b 20 30 50 70 10 0 4 6 9 8 2 3 5 7 1 0 efficiency power loss v in = 12v v out = ?12v pulse-skipping mode burst mode operation
ltc3863 34 3863f for more information www.linear.com/3863 package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.50 ref 1 6 12 7 pin 1 notch r = 0.20 or 0.35 45 chamfer pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (ue12/de12) dfn 0806 rev d 2.50 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 3.30 0.10 0.25 0.05 0.50 bsc 1.70 0.05 3.30 0.05 0.50 bsc 0.25 0.05 de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695 rev d)
ltc3863 35 3863f for more information www.linear.com/3863 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (mse12) 0911 rev f 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ?0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail ?b? 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev f)
ltc3863 36 3863f for more information www.linear.com/3863 ? linear technology corporation 2013 lt 0313 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/3863 related parts typical application part number description comments ltc3864 low i q , high voltage step-down dc/dc controller with 100% duty cycle fixed frequency 50khz to 850khz, 3.5v v in 60v, 0.8v v out v in , i q = 40a, msop-12e, 3mm 4mm dfn-12 ltc3891 60v, low i q , synchronous step-down dc/dc controller pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3890/ltc3890-1 ltc 3890 -2/ ltc 3890 -3 60v, low i q , dual 2-phase synchronous step-down dc/dc controller pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3630 high efficiency, 65v, 500ma synchronous step-down regulator 4v v in 65v, 0.8v v out v in , i q = 12a, 3mm 5mm dfn-16 and msop-16e ltc3834/LTC3834-1 ltc3835/ltc3835-1 low i q , single output synchronous step-down dc/dc controllers with 99% duty cycle pll fixed frequency 140khz to 650khz, 4v v in 36v, 0.8v v out 10v, i q = 30a/80a lt3758a high input voltage, boost, flyback, sepic and inverting controller 5.5v v in 100v, positive or negative v out , 3mm 3mm dfn-10 and msop-10e ltc3826/ltc3826-1 low i q , dual output 2-phase synchronous step-down dc/dc controllers with 99% duty cycle pll fixed frequency 50khz to 900khz, 4v v in 36v, 0.8v v out 10v, i q = 30a ltc3859al low i q , triple output buck/buck/boost synchronous dc/dc controller all outputs remain in regulation through cold crank 2.5v v in 38v, v out(bucks) up to 24v, v out(boost) up to 60v, i q = 28a efficiency gain/phase figure 16. 12v to 40v input, C150v/40ma output, 320khz inverting converter 320khz 39m l1 15h q1 d1 cap 0.47f pgnd ltc3863 3863 f16a ss ith freq sgnd run v in pllin/mode sense gate v fbn v fb 845k 52.3k 1m v out ?150v 40ma 10.7k c in1 : cde afk686m63g24t-f c in2 : murata grm32er71h106h c out1 : tdk cga8p3x7t2e105k/soft c out3 : lelon vej-470m2dtr-1616 d1: on semi mbrs3201t3g l1: toko 1217as-h-150m q1: vishay si7119 v in 12v to 40v c in3 68f 63v c out1 1f 250v 2 c in2 10f 50v 2 c out3 47f 200v 180pf 0.1f 1.8pf 3.3pf 1m + + load current (a) 0.001 40 efficiency (%) power loss (w) 60 90 80 0.01 0.1 3863 f16b 20 30 50 70 10 0 4 6 9 8 2 3 5 7 1 0 efficiency power loss v in = 24v v out = ?150v pulse-skipping mode burst mode operation frequency (hz) 0.1 0 efficiency (%) phase (deg) 10 20 1 10 100 3963 f16c ?10 ?20 40 30 ?5 5 15 ?15 35 25 15 45 75 ?15 ?45 135 105 0 30 60 ?30 120 90 phase gain v in = 24v v out = ?150v gain/phase measurements taken with omicron lab bode 100 vector network analyzer.

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